Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Reexamination Certificate
2007-04-18
2010-10-05
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
C712S217000, C712S032000, C712S214000
Reexamination Certificate
active
07809929
ABSTRACT:
A universal register rename mechanism for instructions with multiple targets using a common destination tag. For each instruction that updates multiple destinations, a single rename entry is allocated to handle all destinations associated with it. A rename entry now consists of a DTAG and a vector to indicate the type of destination(s) that is/are being updated by such a particular instruction. For example, a common DTAG can be assigned to a fixed point unit instruction (FXU) that updates general purpose register (GPR), fixed point exception register (XER), and condition code register (CR) destinations. During flush time, the DTAGs in the recovery link may be used to restore the information indicating that the youngest instruction updates a particular architected register. By using a single, universal rename structure for all types of destinations, a large saving in silicon and power can be realized without the need to sacrifice performance.
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USPTO U.S. Appl. No. 11/736,844, Image File Wrapper printed from PAIR on Apr. 8, 2010, 2 pages.
Le Hung Q.
Nguyen Dung Q.
Sinharoy Balaram
Alrobaye Idriss N
Chan Eddie P
Gerhardt Diana R.
International Business Machines - Corporation
Tkacs Stephen R.
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