Use of a future file for data address calculations in a...

Details Use of a future file for data address calculations in a... Use of a future file for data address calculations in a...

2005-05-24

2005-05-24

Tsai, Henry W. H. (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Commitment control or register bypass

C712S219000

Reexamination Certificate

active

06898695

ABSTRACT:
In an embodiment, a pipelined processor includes a future file for storing updated data address values generated by a data address generator (DAG). These updated values may be provided to the DAG for subsequent address calculation operations.

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patent: 5944810 (1999-08-01), Cherabuddi
patent: 6633970 (2003-10-01), Clift et al.
patent: 20020078326 (2002-06-01), Roth et al.

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