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Intra-instruction fusion

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate

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Introduction sequencer for network structure microprocessor

Electrical computers and digital processing systems: processing – Instruction decoding
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Invalidating instructions in fetched instruction blocks upon pre

Electrical computers and digital processing systems: processing – Processing control – Branching
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IP relative addressing

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to generate an address of a microroutine
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Irregular network

Electrical computers and digital processing systems: processing – Processing architecture
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Isochronous pipelined processor with deterministic control

Electrical computers and digital processing systems: processing – Processing control
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Issue unit for placing a processor into a gradual slow mode...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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Issuing load-dependent instructions in an issue queue in a...

Electrical computers and digital processing systems: processing – Instruction issuing
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Iteratively processing data segments by concurrently...

Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
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