Intra-instruction fusion

Details Intra-instruction fusion Intra-instruction fusion

2006-05-23

2006-05-23

Tsai, Henry W. H. (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate variable length...

C712S244000

Reexamination Certificate

active

07051190

ABSTRACT:
Fusing micro-operations (uops) together. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in cache memory, un-fused, executed in parallel, and retired in order to optimize cost and performance.

REFERENCES:
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 5475824 (1995-12-01), Grochowski et al.
patent: 5530825 (1996-06-01), Black et al.
patent: 5559977 (1996-09-01), Avnon et al.
patent: 5598546 (1997-01-01), Blomgren
patent: 5617549 (1997-04-01), DeLano
patent: 6131158 (2000-10-01), Matsuo et al.
patent: 6199152 (2001-03-01), Kelly et al.
patent: 6330657 (2001-12-01), Col et al.
Zarka Cvetanovic and Dileep Bhandarkar, “Characterization of Alpha AXP Performance Using TP and Spec Workloads”, 1994, Digital Equipment Corp., Boxborough, Mass., USA.

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