Processor architecture scheme which uses virtual address...

Processor configured to select a next fetch address by partially

Processor configured to selectively cancel instructions from...

Processor configured to selectively free physical registers...

Processor core and method for managing program counter...

Processor for processing a program with commands including a...

Processor having a conditional branch extension of an...

Processor having multiple program counters and trace buffers...

Processor having multiple program counters and trace buffers...

Processor having multiple program counters and trace buffers...

Processor having selective branch prediction

Processor including fallback branch prediction mechanism for...

Processor instruction with repeated execution code

Processor instruction with repeated execution code

Processor micro-architecture for compute, save or restore...

Processor provided with a data value prediction circuit and...

Processor that eliminates mis-steering instruction fetch...

Processor that redirects an instruction fetch pipeline immediate

Processor utilizing a loop buffer to reduce power consumption

Processor which executes pipeline processing having a...