Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2000-01-19
2003-07-29
Ellis, Richard L. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S218000, C712S219000
Reexamination Certificate
active
06601162
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a processor, and, more particularly, to a processor which bypasses data upon pipeline processing.
2. Description of the Related Art
FIG. 8
is a diagram showing an internal structure of a conventional processor, and
FIG. 9
is a diagram showing pipeline stages in each pipeline of the processor shown in FIG.
8
.
As shown in
FIG. 9
, the processor of
FIG. 8
has five pipeline stages, namely, “I stage” which is the stage for fetching an arithmetic instruction, “R stage” for decoding an instruction and reading a register out of a register file, “A stage” for an arithmetic operation, “D stage” for accessing a data cache and “W stage” for writing back arithmetic results to the register file. In this processor, the “A stage” is in charge of judging conditions of conditional branch instruction and determine whether branch is taken or not, in addition to arithmetic operation of instructions.
As shown in
FIG. 8
, the processor includes, mainly, an instruction fetch unit
110
, register file
120
, a bypass select logic circuit
130
, two pipelines
140
,
150
, and registers RG
101
through RG
106
.
Those two pipelines
140
,
150
form an arithmetic unit. These two pipelines
140
,
150
can simultaneously execute instructions. That is, this processor is a 2 way super scalar processor.
In the example of
FIG. 8
, the pipeline
140
includes an ALU
142
, registers RG
110
to
113
, and bypass multiplexers
144
,
146
, and executes an ALU arithmetic instruction. The pipeline
150
includes a branch unit
152
, registers RG
120
to RG
122
, and bypass multiplexers
154
,
156
, and executes a branch instruction. Here is shown only ALU
142
and branch unit
152
for simplicity, each of these pipelines
140
,
150
has other arithmetic devices as well.
In the “I stage”, the instruction fetch unit reads out an arithmetic instruction from the instruction cache memory (not shown), then discerns the category of this arithmetic instruction, and sends out an executable instruction to the arithmetic unit. That is, the instruction fetch unit
110
fetches the arithmetic instruction and separates it into the part of instruction and the part of operands. Although not shown in
FIG. 8
, depending on the category of the instruction part of the arithmetic instruction, it sends the ALU instruction to the pipeline
140
having ALU
142
and conditional branch instruction to the pipeline
150
having the branch unit
152
.
On the other hand, the instruction fetch unit
110
outputs source operand numbers Rs
0
R, Rt
0
R, Rs
1
R and Rt
1
R in the operand part of the arithmetic instruction to the register file
120
. That is, the source operand numbers Rs
0
R and Rt
0
R are source operand number of instructions to be issued to the pipeline
140
whereas source operand numbers Rs
1
R and Rt
1
R are numbers of source operands of instructions to be issued to the pipeline
150
.
Additionally, the instruction fetch unit
110
outputs destination operand number Rd
0
R in the operand part of the arithmetic instruction to a register RG
101
. This destination operand number Rd
0
R represents the number of the destination operand of the instruction to be issued to the pipeline
140
. These source operand numbers Rs
0
R, Rt
0
R, Rs
1
R, Rt
1
R and destination operand number Rd
0
R are 5-bit signals. That is, here it is assumed that the processor has 32 registers.
Therefore, instruction mnemonics can be expressed as:
Add Rd, Rs, Rt
In any codes indicating various signals used in the present specification, let the end of each code indicate the stage where the signal has reached. For instance, a destination operand having the number Rd
0
R in the “R stage” gets the number Rd
0
A when reaching the “A stage”.
The instruction fetch unit
110
outputs branch delay slot information BDS
0
R and instruction valid information Valid
1
R. The branch delay slot information BDS
0
R is a signal indicating whether an instruction in the pipeline
140
is that of the branch delay slot of a branch likely instruction or not. The branch delay slot is an instruction positioned just after the conditional branch instruction in a row of instructions. In the example of
FIG. 8
, if an instruction is just after the branch likely instruction, it becomes 1, and otherwise, it becomes 0. In this instruction set architecture (ISA), one instruction existing in the branch delay slot is executed in principle whether the condition of the immediately preceding conditional branch instruction has been established or not. That is, any instruction just after a normal conditional branch instruction is executed unconditionally. However, in the case of a branch likely instruction in this instruction set architecture, one instruction existing in the branch delay slot is not executed when the branch likely instruction is not taken. When it is taken, an instruction in the branch delay slot is executed.
One example of normal conditional branch instructions is shown in FIG.
10
. In
FIG. 10
, Add instruction is an instruction of adding contents of the register r
2
and contents of register r
3
and storing its result in the register r
1
. BNE instruction is an instruction establishing branch when contents of the register Rs and contents of the register Rt are different. That is, when (contents of register r
1
)≠(contents of register r
2
), branch establishes with BNE instruction, and the process returns to Add instruction labeled Loop. However, Sub instruction existing in the branch delay slot is executed even when branch is established. That is, the instruction execution sequence is as follows:
Add → . . . →BNE→Sub→Add.
On the other hand, when the branch instruction is not taken, since the row of instructions is directly executed sequentially, the instruction execution sequence is as follows:
Add → . . . →BNE→Sub→Iw.
Here, Sub instruction is an instruction of subtracting contents of the register r
5
from contents of the register r
4
and storing its result in the register r
3
. Iw instruction is an instruction of loading data from memory whose address is 0+(contents of register r
7
) to the contents of the register r
6
.
The above is the row of execution of the normal conditional branch instruction. Next explained is a row of execution of branch likely instruction.
FIG. 11
is a diagram showing a row of execution of branch likely instruction. As mentioned above, the branch likely instruction is an instruction for executing an instruction in the branch delay slot when branch is established, but not executing the instruction in the branch delay slot when branch is not established.
As shown in
FIG. 11
, BNEL instruction makes branching be established, and causes the process to return the Loop label and execute Add instruction when Rt≠Rs, namely, (contents of register r
1
)≠(contents of register r
2
). Additionally, the Sub instruction in the branch delay slot is executed when branch is established. Therefore, instruction execution sequence is as follows:
Add → . . . →BNEL→Sub→Add
On the other hand, in case of the branch likely instruction, the branch delay slot is not executed when branch is not established. Therefore, the instruction execution sequence is as follows:
Add → . . . →BNEL→Iw
In this manner, branch likely instruction is different from the conditional branch instruction in how to progress the process when branch is not established, and the instruction in the branch delay slot is not executed.
Explanation is returned again to FIG.
8
. Four source operand numbers Rs
0
R, Rt
0
R, Rs
1
R and Rt
1
R sent from the instruction fetch unit
110
in the “R stage” are input to the register file
120
. In the register file
120
, contents of registers corresponding to these source operand numbers Rs
0
R, Rt
0
R, Rs
1
R and Rt
1
R are read out. That is, data contents stored in individual registers are read out, and these data are taken as the source operand.
In this example, the source operan
Ellis Richard L.
Gray Cary Ware & Freidenrich LLP
Kabushiki Kaisha Toshiba
Meonske Tonia L.
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