Stream processing in optically linked super node clusters of...

Stream processing in super node clusters of processors...

Stream processing system having a reconfigurable memory module

Structure of processor having a plurality of main processors and

Sub-pipelined and pipelined execution in a VLIW

Subsystem bridge of AMBA's ASB bus to peripheral...

Super-reconfigurable fabric architecture (SURFA): a...

Superscalar microprocessor configured to predict return addresse

Superscalar microprocessor configured to predict return...

Superscalar microprocessor for out-of-order and concurrently exe

Superscalar microprocessor including a load/store unit,...

Superscalar processor for retiring multiple instructions in work

Superscalar processor with parallel issue and execution device h

Superscalar RISC instruction scheduling

Superscalar RISC instruction scheduling

Superscalar RISC instruction scheduling

Supplying instruction stored in local memory configured as...

Switch complex selectively coupling input and output of a...

Switch coupled function blocks with additional direct...

Switch memory architectures