Superscalar processor for retiring multiple instructions in work

Details Superscalar processor for retiring multiple instructions in work Superscalar processor for retiring multiple instructions in work

1997-06-27

1999-08-31

Coleman, Eric

Electrical computers and digital processing systems: processing

Processing architecture

Superscalar

712 28, 712217, 712218, G06F 938

Patent

active

059448105

ABSTRACT:
In a superscalar processor, multiple instructions are executed in parallel to obtain multiple execution results, and the multiple execution results are stored in a working register file. Each execution result in the working register file has at least one status bit associated therewith which identifies the execution result as valid data. The multiple execution results contained in the working register data then retired by changing the status bits associated with each execution result to identify the execution result as an architectural copy of the data. In this manner, the speculative data is retired without data movement of the speculative data, thus reducing a number of ports needed in the superscalar processor.

REFERENCES:
patent: 5499352 (1996-03-01), Clift et al.
patent: 5613132 (1997-03-01), Clift et al.
patent: 5627985 (1997-05-01), Fetterman et al.
patent: 5689720 (1997-11-01), Nguyen et al.
patent: 5748934 (1998-05-01), Lesartre et al.
patent: 5764943 (1998-06-01), Wechsler

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