Superscalar RISC instruction scheduling

Details Superscalar RISC instruction scheduling Superscalar RISC instruction scheduling

2006-05-23

2006-05-23

Donaghue, Larry D. (Department: 2154)

Electrical computers and digital processing systems: processing

Processing architecture

Superscalar

C712S218000, C712S216000

Reexamination Certificate

active

07051187

ABSTRACT:
A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.

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