Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2004-07-29
2008-08-12
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
07412586
ABSTRACT:
The present invention provides a switch memory architecture (SMA) consisting of: (i) processing elements (PE) (ii) memory banks (MB), and (iii) interconnect switches (ISWITCH). The present invention allows for efficient, potentially unbounded data transfer between two adjacent processes by passing a memory handle and the status registers (memory control information) of the MB. This function may be performed by the ISWITCH.
REFERENCES:
patent: 5522083 (1996-05-01), Gove et al.
patent: 6791939 (2004-09-01), Steele et al.
Gupta Gautam
Rajopadhye Sanjay
Renganarayana Lakshminarayanan
Chan Eddie P
Colorado State University Research Foundation
Fennema Robert E
Lathrop & Gage LC
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