Microprocessor employing and method of using a control bit vecto
Microprocessor with improved out of order support
Multiple issue static speculative instruction scheduling with pa
Pairing of micro instructions in the instruction queue
Parallel computation processor, parallel computation control...
Pipelined asynchronous processing
Pipelined microprocessor and a method relating thereto
Pipelined processor for performing parallel instruction...
Processor architecture providing for speculative execution of in
Processor pipeline including partial replay
Register and instruction controller for superscalar processor
Register file having shared and local data word parts
Register rename stack for a microprocessor
Register renaming in which moves are accomplished by swapping re
Register renaming in which moves are accomplished by...
Register renaming system
Reservation station for a floating point processing unit
RISC microprocessor architecture implementing multiple typed reg
RISC microprocessor architecture implementing multiple typed...
RISC microprocessor architecture implementing multiple typed...