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Pairing of micro instructions in the instruction queue

Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Reexamination Certificate

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Parallel computation processor, parallel computation control...

Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
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Pipelined asynchronous processing

Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
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Pipelined microprocessor and a method relating thereto

Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
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Pipelined processor for performing parallel instruction...

Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
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Processor architecture providing for speculative execution of in

Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
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Processor pipeline including partial replay

Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
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