Processor pipeline including partial replay

Details Processor pipeline including partial replay Processor pipeline including partial replay

1997-12-24

2000-06-13

Coleman, Eric

Electrical computers and digital processing systems: processing

Processing architecture

Superscalar

712219, G06F 1576

Patent

active

060761539

ABSTRACT:
The invention, in one embodiment, is a method for committing the results of at least two speculatively executed instructions to an architectural state in a superscalar processor. The method includes determining which of the speculatively executed instructions encountered a problem in execution, and replaying the instruction that encountered the problem in execution while retaining the results of executing the instruction that did not encounter the problem.

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