Method using vector component comprising first and second...
Method, apparatus, and system for maintaining processor...
Methods and apparatus for exchanging the contents of registers
Methods and apparatus for exploiting virtual buffers to...
Methods and apparatus for reducing the size of code with an...
Methods and apparatus to control functional blocks within a...
Methods and apparatus to minimize the number of stall latches in
Methods and apparatuses for evaluation of regular...
Microprocessor cache redundancy scheme using store buffer
Microprocessor including multiple register files mapped to...
Microprocessor instruction pipeline having inhibit logic at...
Microprocessor with conditional cross path stall to minimize...
Monitoring software pipeline performance on a network on chip
Multi-bit scoreboarding to handle write-after-write hazards...
Multi-branch resolution
Multi-cycle instructions
Multi-threading for a processor utilizing a replay queue
Multicycle NOP
Multiple data hazards detection and resolution unit
Multiport execution target delay queue FIFO array