Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Reexamination Certificate
1998-05-21
2001-08-14
Niebling, John F. (Department: 2812)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
C712S025000
Reexamination Certificate
active
06275928
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to microprocessors and more particularly, in such microprocessors, to a system for organizing the electronic circuits and a method for sequencing the operations performed by these circuits so as to increase the efficiency of the circuits in terms of speed and reduction of electrical consumption.
In a microprocessor, the different instructions of a program are implemented sequentially by periodic electrical signals provided by a clock circuit. The number of cycles of the clock signals needed to perform one instruction varies from one microprocessor to another depending on the manufacturer and type of microprocessor. This number ranges from some cycles to several tens of cycles.
Consequently, microprocessor manufacturers have sought to reduce the number of cycles per instruction to the utmost. This has meant lowering the frequency of the clock signals for a given level of efficiency and, correlatively, reducing the electrical consumption which varies in the same way as the frequency.
2. Description of the Prior Art
At present, the most powerful microprocessors perform an instruction in one half-cycle. However, to achieve a performance level of this kind, they use the techniques known as “pipelining” and “parallelism”. Thus, for example, an instruction is performed in four cycles but during these very same cycles, eight other instructions will be performed in parallel.
Techniques of this kind have the following drawbacks:
the pipelining technique is easy to manage during the running of a linear program but very difficult to manage when a program contains many “conditional branches” or “conditional jumps”, which is the most usual case. For, should there be a conditional branch, the other instructions loaded into the pipeline structure would not be performed. It would therefore become necessary to fill the pipeline structure again, entailing a great loss of efficiency;
an architecture of this kind leads to a greater complexity and to an increase in the volume of the hardware used: this does not make for a sound compromise between the surface area of the integrated circuits and the efficiency of the unit;
an architecture of this kind, following the loss of efficiency due to the pipeline structure and the increase in the volume of hardware leads to a greater electrical consumption.
The object of the present invention therefore is to achieve a system for organizing the electronic circuits of a microprocessor and a method of sequencing the operations performed by these circuits resulting in greater efficiency of the microprocessor, namely in a small number of clock cycles per instruction, a small cycle period, namely a high clock frequency and a low electrical consumption.
SUMMARY OF THE INVENTION
The invention is characterized chiefly by the fact that the loading of each instruction register of each stage of the pipeline structure of the microprocessor is activated by a clock signal, the application of which to the relevant register is conditioned by a signal resulting from the decoding of the instruction contained in the instruction register that precedes it in the chain of the instruction registers.
As a result of this architecture, an instruction register of the chain of registers is activated or loaded by a clock signal only if the instruction contained in the previous instruction register provides for it. Thus, only the instruction registers that are needed for the execution of a program will be activated or loaded.
The invention therefore relates to a microprocessor comprising a chain of instruction registers, wherein at least one output terminal of each instruction register is connected to a decoding circuit, the output terminal of which is connected to the clock signal input terminal of the instruction register that follows it in the chain by means of a logic circuit that receives the clock signal.
The invention relates more specifically to a microprocessor of the type comprising at least one program memory that is addressed by a program counter by means of an addressing circuit and that provides an instruction code at its output terminals when it is addressed, at least one instruction register of the type with loading activated by a clock signal applied to a clock signal input terminal in which the instruction code read in the program memory has to be recorded and a clock circuit that provides clock signals for the sequencing of the operations performed by the microprocessor, wherein an inhibiting device having input terminals and first and second output terminals is associated with each instruction register,
the input terminals of said inhibiting device being connected to the input terminals of the associated register, to the second output terminal of the preceding inhibiting device and to an output terminal of the clock circuit,
the first output terminal of the inhibiting device being connected to the clock signal input terminal of the associated instruction register,
the inhibiting device being designed to provide, at the first output terminal, a signal for the loading of the associated instruction register when the instruction code contains a predetermined combination of digits.
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Earnst, “Long pipelines in single-chip digital signal processors—concepts and case study”, 1/91, pp. 100-108.*
IBM, “Reducing the power dissipation of processors on large CMOS chips”, 7/93, pp. 405-406.*
IMB, “Reducing the power dissipation of processors on large CMOS chips.”, IBM TDB, vol. 36, No. 07, 7/93, pp. 405-406.*
Ernst, Rolf, “Long Pipelines in Single-Chip Digital Signal Processors—Concepts and Case Study,”IEEE Transactions on Circuits and Systems, vol. 38, No. 1, Jan. 1991, New York, pp. 100-108.
“Reducing the Power Dissipation of Processors on Large CMOS Chips,”IBM Technical Disclosure Bulletin, vol. 36, No. 07, Jul. 1993, pp. 405-406.
“Processor Control Using Cycle Types,”IBM Technical Disclosure Bulletin, vol. 28, No. 8, Jan. 1986, pp. 3260-3265.
Arm Claude
Masgonty Jean-Marc
Piguet Christian
Connolly Bove Lodge & Hutz
CSEM Centre Suisse D'Electronique et de Microtechnique S.A.
Niebling John F.
Whitmore Stacy
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