Multi-cycle instructions

Details Multi-cycle instructions Multi-cycle instructions

2000-12-06

2008-12-30

Li, Aimee J (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Reducing an impact of a stall or pipeline bubble

C712S242000, C712S245000

Reexamination Certificate

active

07472259

ABSTRACT:
In one embodiment, a pipelined processor is described that includes an execution pipeline having a plurality of stages and a multi-cycle instruction (MCI) controller adapted to assert a stall signal to stall the multi-cycle instruction within one of the stages of the execution pipeline. The MCI controller is adapted to issue a plurality of instructions to subsequent stages in the pipeline while the multi-cycle instruction is stalled.

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