Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Patent
1998-01-20
1999-09-28
Maung, Zami
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
712215, 712245, G06F 928
Patent
active
059580445
ABSTRACT:
A method for controlling the execution of a microprocessor to cause it to execute a NOP instruction for a programmable number of sequential cycles. A NOP instruction is provided, that includes a predetermined OP code field identifying the NOP instruction as a programmably multiple NOP instruction. A predetermined count field is provided, representing the number of sequential cycles in which a NOP operation is to be performed by said microprocessor. The NOP instruction OP code field is read, as is the NOP instruction count field. In response thereto, a NOP operation is performed for the number of sequential cycles represented by said NOP instruction count field.
REFERENCES:
patent: 4855947 (1989-08-01), Zmyslowski et al.
patent: 5515519 (1996-05-01), Yoshioka et al.
patent: 5546037 (1996-08-01), Kenny et al.
patent: 5727194 (1998-03-01), Shridhar et al.
Brown Richard A.
Seshan Natarajan
Simar Ray
Brady III Wade James
Coulter Kenneth R.
Donaldson Richard L.
Maung Zami
Moore J. Dennis
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