Methods and apparatus to minimize the number of stall latches in

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble

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712235, 713500, 711140, 711169, G06F 900

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active

060386584

ABSTRACT:
The invention comprises in several embodiments a pipeline and a method of operating the pipeline. The pipeline comprises first and second stages each having an output. The first stage is located earlier in the pipeline than the second stage. A first isolation device has an input coupled to the output of the first stage. The first isolation device is for storing data received from the first stage. A second isolation device has an input coupled to the output of the second stage. The second isolation device is for storing data received from the second stage. A stall control is for sending a signal to the first and second isolation devices. The signal is to stall the isolation devices. At least one delay element is connected between the stall control and the second isolation device and is to delay receipt of the signal by the second isolation device.

REFERENCES:
patent: 4382299 (1983-05-01), Dieterich
R. J. Baron and L. Higbie, Computer Architecture (Addison-Wesley Publ. Co. 1994) Chapter 6, pp. 284-297.

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