Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Patent
1998-01-05
2000-03-28
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
712 40, 712206, 712212, G06F 938
Patent
active
060444568
ABSTRACT:
A system and method are described for maintaining synchronization of information propagating through multiple front-end pipelines operating in parallel. In general, these multiple front-end pipelines become asynchronous in response to a stall condition and re-establish synchronization by flushing both front-end pipelines as well as by selectively releasing these front-end pipelines from their stall condition at different periods of time.
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Murty Keshavram N.
Shah Darshana S.
Yeh Tse-Yu
Zaidi Nazar A.
An Meng-Ai T.
Intel Corporation
Nguyen Dzung C.
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