Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Reexamination Certificate
2008-03-14
2011-10-11
Alrobaye, Idriss N (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
C712S220000
Reexamination Certificate
active
08037287
ABSTRACT:
An instruction processing pipeline6is provided. This has error detection and error recovery circuitry20associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline6. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need to be flushed from the instruction pipeline6. Instruction can also be selected for flushing in dependence upon characteristics such as privileged level, number of dependent instructions etc. The instruction pipeline may additionally/alternatively be provided with more than one main storage element26, 28associated with each signal value with these main storage elements26, 28being used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element26, 28to properly capture the signal value corresponding to the following program instruction. In this way flushes can be avoided.
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Great Britain Search Report dated Jun. 6, 2007.
UK Combined Search and Examination Report dated Jul. 22, 2011 for GB 1111036.8.
Bull David Michael
Das Shidhartha
Özer Emre
Alrobaye Idriss N
ARM Limited
Nixon & Vanderhye P.C.
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