Acknowledgement mechanism for just-in-time delivery of load...

Address generation interlock detection

Advanced load address table entry invalidation based on...

Apparatus and method for facilitating out-of-order execution...

Apparatus and method using different size rename registers...

Apparatus for restraining over-eager load boosting in an out-of-

Apparatus, method and system for fast register renaming...

Back-end renaming in a continual flow processor pipeline

Branch instruction execution control apparatus

Comparing operands of instructions against a replay...

Concurrent execution of instructions in a processing system

Control bit vector storage for a microprocessor

Control word register renaming

Controlling writes to non-renamed register space in an...

Data processing system and method for implementing an...

Dependency checking for reconfigurable logic

Different register data indicators for each of a plurality...

Dual-target block register allocation

Dynamic data dependence tracking and its application to...

Dynamic instruction dependency monitor and control system