Control word register renaming

Details Control word register renaming Control word register renaming

2000-09-29

2004-08-17

Treat, William M. (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Scoreboarding, reservation station, or aliasing

C712S222000, C712S228000

Reexamination Certificate

active

06779103

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of processors and more particularly, to a technique for renaming a control word register.
2. Description of the Related Art
In a computer system, a processor operates by responding to program instructions in which microarchitecture op-codes (&mgr;ops), also referred to as machine instructions, control how the processor circuitry responds to the decoded instructions. In some processors, such as processors within the Intel Architecture Family of Processors (which includes the Pentium® processor, manufactured by Intel Corporation of Santa Clara, Calif.), utilize a control word to program how the processor responds to certain instructions. For example, many of the processors of the Intel Architecture Family utilize a separate integer execution unit and a floating point execution unit. In the floating point unit (FPU), a control word register stores a floating point control word (FCW). The FCW value placed in the floating point control word register determines how the floating point unit executes certain instructions. Rounding and precision are two operations which are controlled by the FCW.
In one class of processors of the Intel Architecture Family of Processors, a 16-bit FCW resides in a 16-bit floating point control word register, in which two bits are utilized to control the precision of the floating point operation (such as determining single precision or double precision operation for the data in the floating point registers) and two bits are utilized to control the rounding (such as rounding up, rounding down, or truncating the excess digits). Thus, the FCW value in the FCW register controls how the processor manages the rounding and precision when operating on data in the floating point registers.
Prior art practice utilizes a single FCW register in the floating point unit to control the FPU. Generally, a floating point load control word instruction (FLDCW) is utilized to load the FCW register. Subsequently, &mgr;ops will then cause the processor to operate based on the value of the FCW stored in the FCW register. If, any of the parameters controlled by the current FCW are to be changed, (such as changing the rounding and/or precision), a new FCW value will need to be loaded into the FCW register using the FLDCW instruction. Generally, an FLDCW instruction requires existing pops presently executing in the machine to be completed, before the new FCW value is placed in the FCW register.
One repetitive operation that is used consistently in many processors of the Intel Architecture Family of Processors is the conversion of floating point data to integer data. That is, floating point operations are performed on data in the floating point unit and then converted to integer format for integer operations. In this operation, typically a subroutine is called to convert the floating point value to the integer value. Each time a floating point to integer operation conversion is performed, a new FCW value is typically required in the FCW register since the precision and/or the rounding procedure changes for the different formats. In some instances, after the conversion to integer format, the FCW register needs to be reloaded again with the original FCW to continue operating on floating point data with the proper rounding and precision control. Each time the FCW register is reloaded, an appreciable amount of processor stalling is required since a new FCW value cannot be loaded until all pops requiring the old FCW have completed executing.
The present invention addresses this aspect of the floating point control word register.


REFERENCES:
patent: 5781753 (1998-07-01), McFarland et al.
patent: 5826070 (1998-10-01), Olson et al.
patent: 5951670 (1999-09-01), Glew et al.
patent: 5974525 (1999-10-01), Lin et al.
patent: 5978900 (1999-11-01), Liu et al.
Intel Corporation, “IA-32 Intel Architecture Software Developer's Manual with Preliminary Willamette Architecture Information,” vol. 1: Basic Architecture; 2000.
U.S. patent application Ser. No. 09/472,840; filed Dec. 28, 1999; Clift et al.

Affiliated with

Also associated with

Rating

Control word register renaming does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Control word register renaming, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Control word register renaming will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3293818