Apparatus for restraining over-eager load boosting in an out-of-

Details Apparatus for restraining over-eager load boosting in an out-of- Apparatus for restraining over-eager load boosting in an out-of-

1997-06-25

1999-12-21

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Scoreboarding, reservation station, or aliasing

711167, 712216, 712217, 712 23, G06F 1300

Patent

active

060063262

ABSTRACT:
A system for restraining over-eager boosting of load instructions past store instructions in an out-of-order processor. The system comprises a memory disambiguation buffer for storing load and store instruction addresses and associated data and an instruction scheduling window in operative association with the memory disambiguation buffer. The instruction scheduling window and the memory disambiguation buffer determine load/store dependencies and effectuate replay of the store and load instructions wherein a dependent load instruction has been executed prior to a store instruction. An instruction cache is provided in operative association with the memory disambiguation buffer, together to associate the dependent load instructions with a store instruction such that the store instruction is subsequently executed prior to the dependent load instructions.

REFERENCES:
Sun Microsystems, Inc., "UltraSPARC-II High Performance 64-bit RISC Processor Application Note," Jul. 1996.
Sun Microsystems Computer Corporation, "The SuperSPARC Microprocessor, Technical White Paper," May 1992.
Intel, "Introduction to the Intel Architecture," 1997.
Motorola, Inc., "PowerPC 620 RISC Microprocessor Technical Summary," Jul. 1996.
Cyrix, "6x86MX Processor," May 19, 1997.
Sun Microelectronics, "The UltraSPARC Processor--Technology White Paper," Aug. 27, 1997.
Steven Wallace and Nader Bagherzadeh, Dept. of Electrical and Computer Engineering, University of California, "Multiple Branch and Block Prediction," Feb. 1997.

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