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Scanning modified data during power loss

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Scarfing within a hierarchical memory architecture

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Scatter-gather intelligent memory architecture for...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Scattering and gathering data for faster processing

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Schedulable dynamic memory pinning

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Scheduler for avoiding bank conflicts in issuing concurrent...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Scheduling data frames for processing: apparatus, system and...

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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Scheduling of background scrub commands to reduce high...

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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Scheduling of housekeeping operations in flash memory systems

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Scheduling of housekeeping operations in flash memory systems

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Scheduling of reclaim operations in non-volatile memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Scheduling random I/O for data storage tape

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Scheme for implementing breakpoints for on-chip ROM code...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Scheme for optimal settings for DDR interface

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Scheme for reordering instructions via an instruction...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Scheme for securing a memory subsystem or stack

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Scheme for segregating cacheable and non-cacheable by port...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Scheme to partition a large lookaside buffer into an L2...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Schmoo runtime reduction and dynamic calibration based on a...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Scope-based cache coherence

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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