Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2005-08-02
2005-08-02
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S156000
Reexamination Certificate
active
06925521
ABSTRACT:
The present invention relates to a system and a method for preventing address conflicts when establishing breakpoints and applying one or more patches to code residing on a read only memory (ROM) device. The system and method generally comprises identifying one or more program addresses which require patching, whereby one or more patch addresses are defined; evaluating address bits of the patch addresses and determining index bit positions, whereby address bits occupying the index bit positions define one or more unique tag indices; and storing the index bit positions in a tag programming memory. The system and method may furthermore comprise storing the one or more tag indices and a respectively associated one or more tag addresses in a tag control memory, forming a program index for each program address; associating each program index to a tag index; comparing the tag address associated with the tag index for each matched program index to a predetermined portion of the program address via a comparison circuit; and directing the code to patch instruction data associated with the patch address in a patch memory if the predetermined portion of the program address matches the tag address. The system and method may further comprise a RAM/ROM enable circuit operable to direct the code to the patch memory if the program address originates from the patch memory.
REFERENCES:
patent: 4028678 (1977-06-01), Moran
patent: 4028684 (1977-06-01), Divine et al.
patent: 4141068 (1979-02-01), Mager et al.
patent: 4400798 (1983-08-01), Francis et al.
patent: 4542453 (1985-09-01), Patrick et al.
patent: 4603399 (1986-07-01), Cheek et al.
patent: 5481713 (1996-01-01), Wetmore et al.
patent: 5493674 (1996-02-01), Mizutani et al.
patent: 5546586 (1996-08-01), Wetmore et al.
patent: 5619698 (1997-04-01), Lillich et al.
patent: 5757690 (1998-05-01), McMahon
patent: 5938766 (1999-08-01), Anderson et al.
patent: 5983337 (1999-11-01), Mahalingaiah et al.
patent: 6073252 (2000-06-01), Moyer et al.
patent: 6076134 (2000-06-01), Nagae
patent: 6128751 (2000-10-01), Yamamoto et al.
patent: 6141740 (2000-10-01), Mahalingaiah et al.
patent: 6154834 (2000-11-01), Neal et al.
patent: 6158018 (2000-12-01), Bernasconi et al.
patent: 6260157 (2001-07-01), Schurecht et al.
patent: 6438664 (2002-08-01), McGrath et al.
patent: 2003/0084229 (2003-05-01), Ho et al.
patent: 2003/0217227 (2003-11-01), Parthasarathy et al.
patent: 2004/0049667 (2004-03-01), McCormick et al.
Li Hsiao Yi
Mueller Ryan G.
Tsang Steve K.
Bataille Pierre-Michel
Brady III W. James
Moore J. Dennis
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Scheme for implementing breakpoints for on-chip ROM code... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Scheme for implementing breakpoints for on-chip ROM code..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scheme for implementing breakpoints for on-chip ROM code... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3514506