Scheme for optimal settings for DDR interface

Details Scheme for optimal settings for DDR interface Scheme for optimal settings for DDR interface

2006-09-19

2006-09-19

Bragdon, Reginald G. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S167000, C711S170000

Reexamination Certificate

active

07111111

ABSTRACT:
Methods of optimizing a plurality of numerically controlled delay lines (NCDLS) in a DDR memory controller are presented herein. In one embodiment, a method may comprise, for example, one or more of the following: acquiring a plurality of statistics, the plurality of statistics defining an operating region for the DDR memory controller; and calculating optimal values for the plurality of NCDLs, the optimal values calculated using the plurality of statistics.

REFERENCES:
patent: 6768691 (2004-07-01), Kumazaki et al.
patent: 2005/0010714 (2005-01-01), Kumar et al.

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