Scheme for securing a memory subsystem or stack

Details Scheme for securing a memory subsystem or stack Scheme for securing a memory subsystem or stack

2005-12-08

2008-12-30

Tran, Denise (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S103000, C365S185040, C713S189000

Reexamination Certificate

active

07472244

ABSTRACT:
A scheme for securing a memory subsystem or stack is disclosed. A first memory device performs an authentication on a received operation. If the authentication is valid, a write protect signal to a second memory device is disabled, allowing write or erase operations to be performed on the second memory device.

REFERENCES:
patent: 2004/0049645 (2004-03-01), Lee et al.
patent: 2005/0138314 (2005-06-01), Liang et al.
patent: 2006/0107009 (2006-05-01), Ooshima et al.
U.S. Appl. No. 11/188,254, filed Jul. 22, 2005—Method and Apparatus Capable of Disabling Authenticated Operations and Guaranteed Secure Boot in a Wireless Platform.
U.S. Appl. No. 11/130,759, filed May 17, 2005—Internally Authenticated Flash Remediation.
U.S. Appl. No. 11/237,306, filed Sep. 27, 2005—Secure Booting Form A Memory Device.

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