Use of a translation cacheable flag for physical address...

Details Use of a translation cacheable flag for physical address... Use of a translation cacheable flag for physical address...

1999-12-17

2008-03-25

Tran, Denise (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S206000, C709S250000

Reexamination Certificate

active

07350028

ABSTRACT:
A host coupled to a switched fabric including one or more fabric-attached I/O controllers. Such a host may comprise a processor; a host memory coupled to the processor; and a host-fabric adapter coupled to the host memory and the processor and provided to interface with the switched fabric, which caches selected translation and protection table (TPT) entries from the host memory for a data transaction, and flushes individual cached translation and protection table (TPT) entry in accordance with a translation cacheable flag.

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