User programmable interrupt mask with timeout for enhanced resou

Details User programmable interrupt mask with timeout for enhanced resou User programmable interrupt mask with timeout for enhanced resou

1997-06-03

1999-08-10

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711155, 711163, 711152, 371 572, G06F 1214

Patent

active

059371994

ABSTRACT:
A method and apparatus for implementing a user programmable interrupt mask and timeout count. A master mask latch receives non-privileged instructions which alternatively cause the latch to disable and enable interrupt requests for the processor. The non-privileged disable interrupts instruction additionally causes the initiation of a timeout counter for defining the duration of an interval for which interrupt requests may be disabled. The non-privileged enable interrupts instruction additionally terminates the count of the timeout counter. If the timeout counter is not halted within the defined interval, a system error interrupt is generated, interrupts are re-enabled and the counter is halted. In a further embodiment, the disable interrupts instruction may be incorporated into a fetch and hold instruction and the enable interrupts instruction may be incorporated into a store and release instruction to facilitate atomic read, modify, write operations.

REFERENCES:
patent: 4574350 (1986-03-01), Starr
patent: 4975870 (1990-12-01), Knicely et al.
patent: 5430860 (1995-07-01), Capps, Jr. et al.
patent: 5617556 (1997-04-01), Baumgartner et al.
"Enterprise Systems Architecture/390 Principles of Operation" IBM Publication, SA22-7201-04, Jun. 1997.

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