Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-08-01
2006-08-01
Verbrugge, Kevin (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S206000
Reexamination Certificate
active
07085889
ABSTRACT:
A context identifier is used in a cache memory apparatus. The context identifier may be written into the tag of a cache line or may be written as an addition to the tag of a cache line, during cache write operation. During a cache read operation, the context identifier of as issued instruction may be compared with the context identifier in the cache line's tag. The cache line's data block may be transferred if the context identifiers and the tags match.
REFERENCES:
patent: 5341487 (1994-08-01), Derwin et al.
patent: 5548733 (1996-08-01), Sarangdhar et al.
patent: 5568620 (1996-10-01), Sarangdhar et al.
patent: 5572703 (1996-11-01), MacWilliams et al.
patent: 5581782 (1996-12-01), Sarangdhar et al.
patent: 5615343 (1997-03-01), Sarangdhar et al.
patent: 5710906 (1998-01-01), Ghosh et al.
patent: 5754818 (1998-05-01), Mohamed
patent: 5774700 (1998-06-01), Fisch et al.
patent: 5787490 (1998-07-01), Ozawa
patent: 5796977 (1998-08-01), Sarangdhar et al.
patent: 5809522 (1998-09-01), Novak et al.
patent: 5812803 (1998-09-01), Pawlowski et al.
patent: 5838995 (1998-11-01), Chen et al.
patent: 5844858 (1998-12-01), Kyung
patent: 5903738 (1999-05-01), Sarangdhar et al.
patent: 5919254 (1999-07-01), Pawlowski et al.
patent: 5937171 (1999-08-01), Sarangdhar et al.
patent: 5964856 (1999-10-01), Wu et al.
patent: 5978869 (1999-11-01), Guthrie et al.
patent: 5991855 (1999-11-01), Jeddeloh et al.
patent: 5998023 (1999-12-01), Turkevich et al.
patent: 6012118 (2000-01-01), Jayakumar et al.
patent: 6041380 (2000-03-01), LaBerge
patent: 6065101 (2000-05-01), Gilda
patent: 6081877 (2000-06-01), Taki
patent: 6092156 (2000-07-01), Schibinger et al.
patent: 6108736 (2000-08-01), Bell
patent: 6141747 (2000-10-01), Witt
patent: 6272604 (2001-08-01), Nunez et al.
patent: 6405271 (2002-06-01), MacWilliams et al.
patent: 6427162 (2002-07-01), Mohamed
patent: 6449677 (2002-09-01), Olarig et al.
patent: 6487621 (2002-11-01), MacLaren
patent: 6560690 (2003-05-01), Hum et al.
patent: 6591321 (2003-07-01), Arimilli et al.
patent: 6601121 (2003-07-01), Singh et al.
patent: 6609171 (2003-08-01), Singh et al.
patent: 6615323 (2003-09-01), Petersen et al.
patent: 6675282 (2004-01-01), Hum et al.
patent: 6691118 (2004-02-01), Gongwer et al.
patent: 2001/0007999 (2001-07-01), Rasmussen et al.
patent: 2001/0037424 (2001-11-01), Singh et al.
patent: 2002/0059501 (2002-05-01), McKinney et al.
patent: 2002/0062459 (2002-05-01), Lasserre et al.
patent: 2002/0087795 (2002-07-01), Hum et al.
patent: 2002/0087824 (2002-07-01), Hum et al.
patent: 2002/0147875 (2002-10-01), Singh et al.
patent: 0 706 137 (1996-04-01), None
patent: 1 182 571 (2002-02-01), None
patent: 1215582 (2002-06-01), None
patent: WO 95/24678 (1995-09-01), None
patent: WO 99/36858 (1999-07-01), None
Jim Handy, “The Cache Memory Book—The Authoritative Reference on Cache Design”, Second Edition, Academic Press, 1998.
Picker, Dan, et al. Enhancing SCI's Fairnss Protocol for Increased Throughput, Oct. 19-22, 1993, IEEE 1993 International Conference on Network Protocols, pp. 292-299.
Shanley, Tom, Pentium®Pro and Pentium®II System Architecture, Second Edition, Copyright 1998 by Mindshare, Inc., Addison-Wesley, Boston, San Francisco, New York, Toronto, Montreal, London, Munich, Paris, Madrid, Capetown, Sydney, Tokyo, Singapore, Mexico City, pp. 199-375.
Accelerated Graphics Port Interface Specification Revision 1.0, Jul. 31, 1996, Intel Corporation, 151 pages.
IEEE Standard for a High-Performance Synchronous 32-Bit Bus: MULTIBUS'II, 1988, published by The Institute of Electrical and Electronics Engineers, Inc., New York, NY.
Multibus®II Bus Architecture Specificatioin Handbook, 1984, Intel Corporation, Santa Clara, CA.
Protocol Extensions to Microprocessor Memory Bus to Support Extended Address Space, May 1, 1994, IBM, vol. 37, Issue 5, pp. 389-390.
Baktha Aravindh
Hammarlund Per
Upton Michael D
Venkatraman Venkat K. S.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Verbrugge Kevin
LandOfFree
Use of a context identifier in a cache memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Use of a context identifier in a cache memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Use of a context identifier in a cache memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3609899