Security for logical unit in storage subsystem
Security for logical unit in storage subsystem
Segment descriptor cache addressed by part of the physical addre
Segmenting non-volatile memory into logical pages sized to fit g
Selective address translation for a resource such as a...
Selective address translation in coherent memory replication
Selective address translation in coherent memory replication
Selective address translation in coherent memory replication
Selectively invalidating entries in an address translation...
Selectively mark free frames as unused for cooperative...
Selectively powering X Y organized memory banks
Semiconductor circuit having burst counter circuit which is...
Semiconductor circuit with address translation circuit that...
Semiconductor circuit with address translation circuit that...
Semiconductor device having redundant memory cell arrays and ser
Semiconductor integrated circuit
Semiconductor memory device and memory access system using a fou
Semiconductor memory device and operation method thereof
Semiconductor memory device having adjustable page length...
Semiconductor memory device having advanced tag block