Semiconductor memory device and memory access system using a fou

Details Semiconductor memory device and memory access system using a fou Semiconductor memory device and memory access system using a fou

1996-07-02

1998-11-10

Moore, David K.

Electrical computers and digital processing systems: memory

Address formation

Varying address bit-length or size

711220, 711202, 36523002, 36523003, 36523006, 36523008, G06F 926, G06F 1202, G06F 1210

Patent

active

058359664

ABSTRACT:
The disclosed is an DRAM which is accessible in response to four-state address signal. A two-state address signal generator receives the four-state address signal respectively defined by four voltage levels and converts it to a row address signal and a column address signal which are two-state address signals. Converted address signals are supplied to a row decoder and a column decoder, respectively. Address signals for access are supplied without adopting an address multiplexing system, so that it is possible to perform accurate addressing under the requirement of high speed operation. In addition, the number of sense amplifiers to be activated in one read operation can be reduced, and therefore power consumption can be also reduced.

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