Segmenting non-volatile memory into logical pages sized to fit g

Details Segmenting non-volatile memory into logical pages sized to fit g Segmenting non-volatile memory into logical pages sized to fit g

1996-10-15

1998-06-09

Swann, Tod R.

Electrical computers and digital processing systems: memory

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Address mapping

711173, 711153, 711103, 39518201, G06F 1206, G06F 1216

Patent

active

057652112

ABSTRACT:
An electronic component including an electrically erasable non-volatile memory for storing information structured in logical entities that are managed by a memory manager. The memory is segmented into pages for the purpose of erasing the information. The memory manager is programmed to organize at least one type of logical entity into pages. Each of the logical entities occupies, at least in part, an integer number of pages in an exclusive manner. This technique is applicable to electronic components to which the electrical power supply is liable to be interrupted in an untimely manner.

REFERENCES:
patent: 3970999 (1976-07-01), Elward
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patent: 5185720 (1993-02-01), Vaillancourt et al.
patent: 5210854 (1993-05-01), Beaverton et al.
patent: 5371876 (1994-12-01), Ewertz et al.
patent: 5430856 (1995-07-01), Kinoshita

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