Electrical computers and digital processing systems: memory – Address formation – Incrementing – decrementing – or shifting circuitry
Reexamination Certificate
1997-12-12
2001-04-03
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Incrementing, decrementing, or shifting circuitry
C711S217000, C711S218000, C365S189020, C365S189120, C365S230020, C365S230080
Reexamination Certificate
active
06212615
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor circuit, and particularly to a burst address generating circuit of a synchronous memory circuit with a burst transfer function.
As a high speed data transfer system following an operation speed of a CPU for making a high-performance computer system, there is a burst data transfer system. This is a system in which after a base address is given to a synchronous memory, addresses are automatically generated in the memory by a clock signal (abbreviated “CLK”), so that data is outputted at high speed. An address sequence for generation of a burst signal is different according to a system in which a memory is used.
At present, as a high speed memory equipped with a burst function, there is a synchronous static random access memory (abbreviated “SSRAM”) which is used as a cache memory, and an interleave system is used as a burst sequence. Table 1 shows the sequence.
TABLE 1
External input address
Add0
Add1
Add2
—
—
First burst address
{overscore (Add0)}
Add1
Add2
—
—
Second burst address
Add0
{overscore (Add1)}
Add2
—
—
Third burst address
{overscore (Add0)}
{overscore (Add1)}
Add2
—
—
In this case, two bits of Add
0
and Add
1
of the least significant bit constitute a burst address, and on the basis of an external input address, only the address Add
0
is changed to the reverse phase in the first burst cycle, only the address Add
1
is changed to the reverse phase in the second burst cycle, and both of address Add
0
and Add
1
are changed to the reverse phase in the third burst cycle, while the address Add
2
and the following hold the data as they are in the burst cycles. A circuit for realizing this operation will be hereinafter described.
FIG. 1
shows a first example of a conventional circuit. Burst address Add
0
and Add
1
are inputted into register circuits RG, respectively. The register circuit RG acquires the burst address Add
0
and add
1
at a rising edge of a control clock signal EK and outputs the burst address. The register circuit RG holds the output data until a next clock edge of the control clock signal EK receives. The output is changed to positive
egative operation signals by an inverter circuit, and either one is selected by a multiplexer MUX
0
into internal address information A
0
. The information A
0
and its inverse information A
0
as its inverted signal are inputted into a decoder DEC
1
, and in this case, one of output signals B
1
through B
4
is selected as a ¼ selection signal. The control clock signal EK for controlling the register RG is generated by an AND logic circuit EKB of an internal clock signal K synchronous with an external input clock signal CLK and a base address acquisition mode signal E from the outside. The internal control signal K and the mode signal E are also simultaneously inputted into an address logic control circuit BCC
0
at a burst time, and when the mode signal E is low in the burst, the circuit controls and switches the multiplexer MUX
0
synchronously with the internal clock signal K. The address logic control circuit BCC
0
is constructed as a counter circuit for generating a signal to invert the address Add
0
for every cycle of the internal clock signal K, and a signal to invert the address Add
1
for every two cycles thereof.
The operation will now be described. Since the mode signal E becomes high at the input of an external address, the signal EK alters like the internal clock signal K, so that the data Add is acquired synchronously with the internal clock signal K. At this time, since the multiplexer MUX
0
is fixed and allows the positive logic to path, the address Add
0
is inputted into the decoder DEC
1
with its logic unchanged. Since the mode signal E becomes low at the generation of the burst address, the control clock signal EK is fixed at low, the register RG outputs the final data held at the external address input before the burst. At the same time, since the circuit BCC
0
generates a switching signal for the multiplexer MUX
0
synchronously with the internal clock signal K, the burst cycle can be realized in which inverted address Add
0
or inverted address Add
1
with respect to the base address of Add
0
and Add
1
is generated in the interleave sequence.
Next, a second conventional example in which a decoder circuit is placed in front of an input register so that a burst signal is generated after completion of ¼ selection by the decoder circuit, will be described. Four select signals B
1
through B
4
are produced by decoding the address Add
0
and Add
1
and one select signal is selected among the four select signals B
1
to B
4
. The selection of selected signals is as shown in Table 2 in the burst sequence of the interleave mode. For example, in the case where both of the address Add
0
and Add
1
are low, the signal B
1
is selected at the external input cycle, and at the burst cycles subsequent thereto, the signals B
2
, B
3
and B
4
are sequentially selected.
TABLE 2
External input
Add0, Add1
0,0
1,0
0,1
1,1
External input
Selected signal
B1
B2
B3
B4
First burst
Selected signal
B2
B1
B4
B3
Second burst
Selected signal
B3
B4
B1
B2
Third Burst
Selected signal
B4
B3
B2
B1
FIG. 2
shows an example of a conventional circuit for realizing this burst counter circuit. There are four NOR decoder circuits DEC
1
with inputs of positive
egative signal A
0
or inverted A
0
, and signal A
1
or inverted A
1
of each of the address Add
0
and Add
1
, and their outputs X
1
through X
4
are respectively inputted into registers RG. Like the first conventional example, a signal EK for controlling the registers RG is generated by an AND logic circuit EKB of a base address acquisition mode signal E and an internal clock signal K. The outputs E
1
through E
4
of the register circuits RG are outputted as signals B
1
to B
4
through multiplexers MUX into an internal circuit, and at the same time, are inputted into second register circuits RG
1
with the signal K. Outputs B
1
R to B
4
R of these register circuits RG
1
inputted to the multiplexers on other paths. For example, the multiplexer MUX with input of the output signal E
2
has other two inputs of the signals B
1
R and B
3
R, and a switching signal flux BC for the inputs is composed of signals FB, RB and EB. The signal flux BC of a circuit BCC
2
is composed of the signal FB of an OR logic output of the signals E
1
and E
2
, the signal RB of an OR logic output of the signals E
2
and E
4
, and the signal EB of the same logic as the signal E.
The operation of this circuit will be described. One of decode signal outputs X
1
through X
4
corresponding to two addresses becomes high and is selected, and the others are low to be in non-selected state and are inputted into the registers RG. For example, when the signal X
1
is selected and the signal E becomes high at external address acquisition, the signal EK is inputted into the register RG synchronously with a rising edge of the clock signal K, and the registers acquire the data of the signals X
1
through X
4
. At the same time, the data is outputted as the signals E
1
through E
4
. Since the signal EB is high, the multiplexer MUX is changed so that the signal E
1
is outputted as the signal B
1
as it is. The signal B
1
is transferred to an internal memory circuit such as a next stage decoder. Next, when the burst mode is established, the signal E becomes low, and the signal EK is fixed at low and does not alter, so that the signals E
1
through E
4
as input register data are fixed. Since the signal E
1
is selected and is high, the signal FB becomes high, and the signals RB and EB become low, so that the multiplexer MUX changes selection to the feedback signal (signal B
4
R for signal E
1
) from an adjacent path. The data of the signals B
1
through B
4
in the previous cycle is received into the burst counter register RG
1
by the clock signal K, and at the same time, the data is outputted as the signals B
1
R through B
4
R, so that this signal is outputted to B
1
through B
4
through the multiplexer on a
NEC Corporation
Nguyen Hiep T.
Sughrue Mion Zinn Macpeak & Seas, PLLC
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