Semiconductor device having redundant memory cell arrays and ser

Details Semiconductor device having redundant memory cell arrays and ser Semiconductor device having redundant memory cell arrays and ser

1997-07-30

2000-04-18

Cabeca, John W.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711 5, 365200, 714 7, G06F 1208

Patent

active

060527676

ABSTRACT:
In order to prevent a delay in the judgement of a judging result obtained by determining whether a memory cell specified by address signals supplied serially from the outside is a defective memory cell, a semiconductor device includes a memory cell array having a plurality of memory cells for writing data to and reading the same from an address specified by the external address signals. Data are written into and read from redundant memory cell arrays in place of a defective memory cell when the defective memory cell exists in the memory cell array. A judging circuit judges whether or not an input address corresponds to an address of the defective memory cell. In the semiconductor memory to which addresses are serially inputted, the judging circuit sequentially judges whether or not the serially-input addresses are addresses of defective memory cells.

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