Two address map for transactions between an X-bit processor...

Two address map for transactions between an X-bit processor...

Two level address translation and memory registration system and

Universal PTE backlinks for page table accesses

Updating and invalidating store data and removing stale...

User interface system for a multi-protocol storage appliance

Using an IOMMU to create memory archetypes

Using current recovery mechanisms to implement dynamic...

Using short references to access program elements in a large...

Using vector processors to accelerate cache lookups

Very high speed page operations in indirect accessed memory...

Virtual address bypassing using local page mask

Virtual address cache and method for sharing data using a...

Virtual address to physical address translation of pages with un

Virtual address translation system with caching of...

Virtual address window for accessing physical memory in a comput

Virtual linear frame buffer addressing method and apparatus

Virtual memory address translation control by TLB purge...

Virtual memory address translation mechanism with controlled...

Virtual memory management