Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1998-03-05
2000-09-26
Gossage, Glenn
Electrical computers and digital processing systems: memory
Address formation
Address mapping
711153, 711208, 711220, 711202, 345515, 345517, 345512, G06F 1206, G06F 1210, G09G 536
Patent
active
061254371
ABSTRACT:
A virtual linear frame buffer addressing method and apparatus efficiently convert a linear address supplied by an application programming (API) into an X, Y address used in a rectangular memory addressing arrangement. The virtual linear frame buffer addressing logic allows rectangular memory addressing to coexist in an environment that requires the use of linear memory addressing by creating a table of address ranges, byte stride values and physical address offset descriptors. The address ranges and byte stride values are associated with particular sections of frame buffer memory. An offset descriptor is associated with each section of physical memory. The address ranges, byte stride values and offset descriptors are placed into a table. When a linear address is received from an API, the address range is determined. The lower bound of the address range is the base address. The base address is subtracted from the linear address resulting in a local linear address. Based upon the address range, a particular byte stride value is selected from the table and used to divide the local address resulting in an X, Y location corresponding to the linear address. The X, Y location and the offset descriptor are supplied to a memory controller, such as a graphics memory controller, which then determines the physical address corresponding to the linear address.
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Gossage Glenn
Hewlett--Packard Company
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