Virtual memory address translation control by TLB purge...

Details Virtual memory address translation control by TLB purge... Virtual memory address translation control by TLB purge...

2006-10-03

2006-10-03

Peikari, B. James (Department: 2189)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S202000, C711S206000, C711S208000

Reexamination Certificate

active

07117338

ABSTRACT:
In a computer system, an architecture is disclosed for optimizing aspects of data movement operations by performing functions such as memory allocation and notification on hardware rather than software. In this environment, the claimed invention is a method and apparatus for ensuring the integrity of data movement operations from virtual memory. The invention monitors and detects Translation Lookaside Buffer (“TLB”) purges, a hardware-based operation whose occurrence signals that virtual-to-physical mapping has changed. Responsive to detection of a TLB purge during the set up or execution of a data movement operation, the claimed invention aborts the operation, and then enqueues corresponding completion status information to notify processors of the event.

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