Cooperative interconnection for reducing port pressure in...

Cooperative lock override procedure

Cooperative processing of tasks in a multi-threaded...

Cooperative scheduling for multiple consumers

Coordination of quality of service in a multi-layer...

Coprocessor-integrated packet-type memory LSI, packet-type...

Copy protection system only authorizes the use of data if...

Core clock alignment circuits that utilize clock phase...

Core logic device of computer system

Core logic unit with internal register for peripheral status

Correlating high-speed serial interface data and FIFO status...

Counter updating system using an update mechanism and...

Counting a number of occurrences of a first RTS (ready to...

Coupling a specialty system, such as a metering system, to...

Coupling data buffers with memory interfaces

Coupling device for connectors wherein coupling device...

Covert channel for conveying supplemental messages in a...

CPU address decoding with multiple target resources

CPU contained LSI

CPU expandability bus