Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-04-14
2002-01-08
Beausoleil, Robert (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C710S120000, C711S105000
Reexamination Certificate
active
06338108
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a packet-type memory LSI which is provided with one or more built-in on-chip coprocessors (i.e. a coprocessor-integrated packet-type memory LSI), and a packet-type memory/coprocessor bus for connecting the coprocessor-integrated packet-type memory LSIs with the bus master.
DESCRIPTION OF THE PRIOR ART
Generally, memory LSIs are increasingly required accessibility with wider data bandwidth if storage capacities of the memory LSIs become larger. This will be easily understood by analogy with a bag in which a lot of articles are stored. Suppose the size of a bag is made larger and larger, and meanwhile the size of its opening remains the same, the bag is necessitated to become more and more inconvenient for storing and taking out the articles. Similarly, suppose the storage capacity of a memory LSI is made larger and its data bandwidth remains the same, the memory LSI will become very unusable for writing and reading data. Therefore, it is very important to keep the balance between the storage capacity and the data bandwidth in order to realize a memory LSI which is usable in a system, and thus development for extending the data bandwidth is growingly promoted mainly on DRUMs which are memory LSIs having the largest storage capacity.
In order to extend the data bandwidth, the operating frequency of the interface between the memory LSI and external devices has to be increased as high as possible, in which simultaneous operation of external I/O signal terminals becomes an obstacle. In the case where a plurality of signal terminals are operating simultaneously at high speed, power consumption of the memory LSI chip becomes high and intense switching noise occurs, and thereby operation errors are caused. Further, when the number of external I/O signal terminals is large, timing skews between the external I/O signal terminals tend to occur and timing adjustment becomes difficult, and thus the high speed operation of becomes difficult.
For such reasons, there have been developed some techniques in order to realize the wider data bandwidth of DRAMs. In such techniques, the number of signal lines in a memory bus to which a DRAM is connected is reduced, and the number of terminals in the external I/O signal terminal of a DRAM is reduced, and the operation frequency of the memory bus is increased. Typical examples of such DRAMs are Rambus DRAMs, SLDRAMs (formerly known as SyncLink DRAMs), Mediachannel DRAMs, etc. Detailed description of the Rambus DRAMs are given in a variety of manuals published by Rambus Inc. The SLDRAMs are now on construction of their specifications as standardized techniques in the IEEE by the SLDRAM Consortium (former SyncLink Consortium), and tentative specifications are shown in “SLDRAM: High-Performance, Open-Standard Memory”, IEEE Micro November/December 1997, pp.
29-39=l , or “Draft Standard for A High-Speed Memory Interface (SLDRAM)”, Draft
099 P1596.7-199x (http://www.sldram.com/Documents/SyncLinkD0
—
99.pdf). And with regard to the Mediachannel DRAMs, detailed description is given in a paper which has been presented in a well-known international conference COMPCON'96 (Spring): Tim Robinson et al. “Multi-Gigabyte/sec DRAM with the MicroUnity Mediachannel Interface”, Proc. of COMPCON'96 (Spring), pp.378 (1996).
In DRAMs employing such techniques, memory bus techniques or DRAM interface techniques called ‘packet-type’ or ‘protocol-type’ are adopted in order to realize effective DRAM access as well as realizing the small number of the signal lines and the small number of terminals in the external I/O signal terminal. Therefore, DRAMs and memory buses according to such conventional techniques will be hereafter referred to as ‘packet-type DRAMs’ and ‘packet-type memory buses’, respectively.
In the following, description will be given on the packet-type DRAM and the packet-type memory bus.
FIG. 1
is a block diagram showing an example of composition of a conventional packet-type DRAM
1001
. In
FIG. 1
, the packet-type DRAM
1001
comprises a memory section
11
, a control section
1012
, and an interface section
13
.
The memory section
11
consists of a DRAM core section
15
and a memory control register section
16
. The DRAM core section
15
is composed of a plurality of DRAM banks
17
and a plurality of sense amplifiers
18
which are provided corresponding to each of the DRAM banks
17
, and the memory control register section
16
includes a plurality of memory control registers
29
.
The control section
1012
includes a memory control logic circuit
1019
, a control signal register
20
, a write data register
21
, a read data register
22
, and a memory device ID verification circuit
1023
. The control section
1012
is provided with three I/O signal terminals to be connected with the interface section
13
. The I/O signal terminals of the control section
1012
include a control signal terminal
24
and a write data terminal
25
(input terminals) and a read data terminal
26
(output terminal).
The interface section
13
is connected with an external I/O terminal
5
. The memory section
11
and the control section
1012
are connected together by an internal memory data bus
27
which is a bidirectional bus.
FIG.
2
A through
FIG. 2C
are block diagrams showing examples of connections between the conventional packet-type DRAM
1001
and a microprocessor
9
via a packet-type memory bus
1002
. Three types of connections are shown in FIG.
2
A through FIG.
2
C. The packet-type memory bus
1002
is a single bus master type bus and only one bus master is allowed to exist on the packet-type memory bus
1002
. All of the packet-type DRAMs
1001
connected to the packet-type memory bus
1002
operate as slave devices. Here, the word ‘bus master’ generally means a device which can exclusively control a bus and send requests to the bus, and the word ‘slave device’ generally means a device which does not spontaneously send requests to the packet-type memory bus
1002
but only responds to the request from the bus master. As will be explained, by allowing only one bus master on the bus, the bus master can send a request without arbitration for the bus exclusive ownership of the packet-type memory bus
1002
, thereby the protocols for the packet-type memory bus
1002
can be simplified. Incidentally, although the microprocessor
9
is provided as the bus master of the packet-type memory bus
1002
in FIG.
2
A through
FIG. 2C
, other type of a bus master can be provided to the packet-type memory bus
1002
, such as a memory controller, a signal processor, a graphics accelerator, an ASIC of other type, etc.
In the composition of
FIG. 2A
, in the same way as the packet-type DRAM
1001
of
FIG. 1
, the packet-type DRAM
1001
of
FIG. 2A
is composed of a memory section
11
, a control section
1012
, and an interface section
13
. All of the I/O terminals of the control section
1012
, i.e. the control signal terminal
24
, the write data terminal
25
and the read data terminal
26
, are connected to the interface section
13
. The interface section
13
is connected to the packet-type memory bus
1002
via the external I/O terminal
5
. The packet-type memory bus
1002
connects the microprocessor
9
and the packet-type DRAMs
1001
. The packet-type memory bus
1002
in
FIG. 2A
is a bidirectional bus.
In the composition of
FIG. 2B
, the interface section
13
is composed of a control interface section
13
-
1
and a data interface section
13
-
2
. The control signal terminal
24
of the control section
1012
is connected to the control interface section
13
-
1
, and the write data terminal
25
and the read data terminal
26
of the control section
1012
are connected to the data interface section
13
-
2
. The packet-type memory bus
1002
of
FIG. 2B
is composed of a control bus
1002
-
1
and a data bus
1002
-
2
. The control interface section
13
-
1
is connected to the control bus
1002
-
1
, and the data interface section
13
-
2
is connected to the data bus
1002
Beausoleil Robert
McGinn & Gibb PLLC
Phan Raymond N
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