Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2005-01-04
2005-01-04
Park, Ilwoo (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S033000, C710S034000, C710S058000, C710S104000
Reexamination Certificate
active
06839779
ABSTRACT:
An apparatus for limiting a data transfer bandwidth through handshake suppression is configured to generate a first reset signal, generate a second reset signal a predetermined number of clock cycles after generating the first reset signal, generate a handshake count representing a number of receptions, between the first reset signal and the second reset signal, of a first Ready to Send (“RTS”) handshake signal and a first Ready to Receive (“RTR”) handshake signal, and disable a second RTR handshake signal and the first RTS handshake signal based on a comparison of the handshake count and a maximum value.
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Copy of search report dated Nov. 20, 2002.
Simpson David Leon
Velez Didier Joseph Marie
Duffy Vincent E.
Park Ilwoo
Thomson Licensing S.A.
Tripoli Joseph S.
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