CPU address decoding with multiple target resources

Details CPU address decoding with multiple target resources CPU address decoding with multiple target resources

2006-10-03

2009-08-04

Tsai, Henry W. H. (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output addressing

C365S236000

Reexamination Certificate

active

07571260

ABSTRACT:
A microcomputer includes a CPU, multiple resources, and an output circuit having an address decoder. The CPU outputs an address signal to the address decoder. The address decoder decodes the address signal and the output circuit outputs a select signal to at least one of the resources in accordance with the decoded address signal. Each of the resources is writable by the CPU when receiving the select signal. When the address signal indicates a predetermined address, the output circuit outputs the select signal to at least two of the resources at a time. Thus, data can be written to the multiple resources at a time. Therefore, the CPU can write the data to the multiple resources within a reduced time by using the output circuit.

REFERENCES:
patent: 5335336 (1994-08-01), Kametani
patent: 2003/0112670 (2003-06-01), Oberlaender et al.
patent: A-2004-362176 (2004-12-01), None

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