Locking of computer resources
Lockless access to a ring buffer
Logic arrangement, system and method for configuration and...
Logic configured for complimenting data on a bus when...
Logic flag registers for monitoring processing system events
Logic gateway circuit for bus that supports multiple...
Logical address direct memory access with multiple...
Logical output queues linking buffers allocated using free lists
Logical partition hosted virtual input/output using shared...
Logical PCI bus
Logical volume selection in a probability-based job scheduler
Logical-to-physical lane assignment to reduce clock power...
Logical-to-physical lane assignment to reduce clock power...
Long latency interface protocol
Long latency interface protocol
Long latency interrupt handling and input/output write posting
Long-distance synchronous bus
Long-distance synchronous bus
Long-haul PCI-to-PCI bridge
Look ahead split release for a data bus