Logical address direct memory access with multiple...

Details Logical address direct memory access with multiple... Logical address direct memory access with multiple...

2011-01-25

2011-01-25

Kindred, Alford W (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S022000

Reexamination Certificate

active

07877524

ABSTRACT:
A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.

REFERENCES:
patent: 6732198 (2004-05-01), Johnson et al.
patent: 7716389 (2010-05-01), Bruce et al.
patent: 2005/0149632 (2005-07-01), Minami et al.
patent: 2006/0190689 (2006-08-01), Van Niekerk

Affiliated with

Also associated with

Rating

Logical address direct memory access with multiple... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logical address direct memory access with multiple..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logical address direct memory access with multiple... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2735938