Logic gateway circuit for bus that supports multiple...

Details Logic gateway circuit for bus that supports multiple... Logic gateway circuit for bus that supports multiple...

2007-10-31

2010-06-22

Rinehart, Mark (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

C710S306000, C710S313000

Reexamination Certificate

active

07743193

ABSTRACT:
A logic gateway circuit is provided for a bus to support multiple interrupt request signals, including an output OR gate having a plurality of input terminals and an interrupt request signal output signal, an inverter having an input terminal connected to the interrupt request signal output terminal of the output OR gate and an output terminal, and a plurality of gateway circuits to respectively and selectively device-end interrupt request signals generated by a plurality of target devices to transmit through the gateway circuit to the output OR gate or to queue the device-end interrupt request signals in the gateway circuit. Each gateway circuit includes an AND gate and an OR gate, wherein the OR gate bases on the states of an output terminal of the AND gate and the interrupt request signal output terminal of the output OR gate to generate a gateway signal to a gateway signal input terminal of the AND gate.

REFERENCES:
patent: 5951669 (1999-09-01), Bailey et al.
patent: 6085279 (2000-07-01), Suzuki
patent: 6192442 (2001-02-01), Haren et al.
patent: 6263395 (2001-07-01), Ferguson et al.
patent: 6401154 (2002-06-01), Chiu et al.
patent: 6772257 (2004-08-01), Futral
patent: 7054974 (2006-05-01), Quach et al.
patent: 7181559 (2007-02-01), Barth et al.
patent: 2005/0071531 (2005-03-01), Oshins
patent: 2006/0265536 (2006-11-01), Chen
patent: 1938686 (2007-03-01), None
patent: 0786726 (1996-12-01), None
patent: 0840226 (1998-05-01), None
Shanley, T., et al.; “ISA System Architecture”; Mindshare, Inc.; Feb. 2000; pp. 365-367, 391-395; XP002501309.
Communication from the European Patent Office dated Nov. 12, 2008 with regard to the corresponding foreign application EP08000838.

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