Logical-to-physical lane assignment to reduce clock power...

Details Logical-to-physical lane assignment to reduce clock power... Logical-to-physical lane assignment to reduce clock power...

2008-05-06

2008-05-06

Phan, Raymond N (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S305000, C710S310000

Reexamination Certificate

active

07370132

ABSTRACT:
A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, clock buffers not required to drive active data lanes are placed in an inactive state to reduce clock power dissipation.

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Gerald Holzhammer, Intel, Developer Update Magazine, “Creating a Third Generation I/O Bus,” Sep. 2001, pp. 1-5, Copyright © Intel Corporation 2001.
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