Flexibility of design of a bus interconnect block for a data...
Hardware speed selection behind a disk array controller
High-speed dynamic multi-lane deskewer
High-throughput interface between a system memory controller and
High-throughput interface between a system memory controller...
Innovative dual-channel serial interface circuit scheme
Input device for information terminal
Input/output cell with a programmable delay element
Interconnection architecture for managing multiple low...
Interface apparatus and packet transfer method
Low overhead, data transparent synchronization of streaming...
Managing the copying of writes from primary storages to...
Master isochronous clock structure having a clock controller...
Memory controller which increases bus bandwidth, data...
Memory device having a controller capable of disabling data...
Memory management system having a linked list processor
Memory outputting both data and timing signal with output...
Memory system and method for setting data transmission speed...
Method and apparatus for asynchronous communication over a...
Method and apparatus for budget development under universal...