Memory controller which increases bus bandwidth, data...

Details Memory controller which increases bus bandwidth, data... Memory controller which increases bus bandwidth, data...

2005-08-16

2005-08-16

Huynh, Kim (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output process timing

C710S052000, C711S149000

Reexamination Certificate

active

06931462

ABSTRACT:
A memory controller increases the effective bus bandwidth of a computer system. The memory controller includes a first port and a second port which receive and transmit N-bit data values, respectively; a third port receiving and transmitting 2N-bit data values; and a fourth port and a fifth port receiving and transmitting the N-bit data values, respectively. Here, two N-bit data values are simultaneously fetched from a memory device corresponding to the first port via the first port and a memory device corresponding to the second port in response to a command signal and an address input via the third port, the two fetched N-bit data values are combined into a 2N-bit data value, and the 2N-bit data value is transmitted to the third port. In addition, an N-bit data value is fetched from a corresponding memory device via the first port and/or second port in response to a command signal and address input via the fourth port and/or fifth port, and the fetched N-bit data value is transmitted to the fourth port and/or fifth port.

REFERENCES:
patent: 5475437 (1995-12-01), Song
patent: 5687102 (1997-11-01), Thomson
patent: 6715094 (2004-03-01), Jacobs
patent: 6732247 (2004-05-01), Berg et al.
patent: 6820167 (2004-11-01), Naffziger et al.

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