Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2004-02-12
2010-10-19
Kindred, Alford W (Department: 2181)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S032000, C710S045000, C710S052000, C709S234000
Reexamination Certificate
active
07818479
ABSTRACT:
A device interface circuit unit transfers a command and data in packet format between the unit and the host. A transport layer is provided with a receive FIFO, a command detection circuit and a send FIFO, and an application layer is provided with a receive task file register and a send task control file register. An available time is generated for each break point of a packet during data transfer in order to receive another command packet from the host. When the command packet is received from the host in the available time during data transfer, the data transfer is suspended and the received command is decoded to execute a process for continuing or canceling the data transfer, after which the data transfer is resumed.
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Matsubayashi Sumie
Myoga Nobuyuki
Sugahara Hirohide
Takeuchi Katsuhiko
Utsunomiya Shin-ichi
Abad Farley J
Greer Burns & Crain Ltd.
Kindred Alford W
Toshiba Storage Device Corporation
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