Memory management system having a linked list processor

Details Memory management system having a linked list processor Memory management system having a linked list processor

2007-01-09

2007-01-09

Peikari, B. James (Department: 2189)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output process timing

C710S029000, C710S036000, C710S052000, C710S058000, C711S167000

Reexamination Certificate

active

10699315

ABSTRACT:
A memory management system adapted to process linked list data files. The system has a plurality of low storage capacity high speed memories and a lower speed high storage capacity bulk memory. An access flow regulator generates requests for the reading and writing of linked list files by the memories. The head and tail buffers and at any intermediate buffers of a linked list are written into the high speed memories. The intermediate buffers are immediately transferred from the high speed memories to said bulk memory while leaving the head buffer and the tail buffer of the linked list in the high speed memories. In read operations, the head and tail buffers are read from the high speed memories. The intermediate buffers are transferred from the bulk memory to said the high speed memory and then read from the high speed memories.

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